The present invention relates generally to a semiconductor integrated circuit having a spread spectrum clock generator (SSCG) and particularly to the self-diagnosis of the same semiconductor integrated circuit.
The SSCG is a clock generator that modulates a clock frequency in a manner varying over time. The SSCG is mounted mostly over digital LSI's as a clock generator for suppressing unnecessary electromagnetic radiation from the semiconductor integrated circuit. Generally, the SSCG is configured by adding a modulation circuit to a PLL circuit to which a reference clock is input and which multiples the frequency. There are two types of spread modulation, center-spread modulation and down-spread modulation, relative to a center frequency obtained by suitably multiplying the reference clock frequency. Center-spread modulation involves modulating the frequency symmetrically above and below the center frequency. Down-spread modulation involves modulating the frequency only on the low-frequency side, with the highest frequency established by suitably multiplying the reference clock frequency.
Meanwhile, the self-diagnostic function for semiconductor integrated circuits is important because their test cost is on the increase as a result of their ever-increasing degrees of integration. In particular, it is very important for the SSCG to possess a self-diagnostic function that may replace otherwise-necessary special equipment such as a spectrum analyzer of which the measuring time tends to be prolonged.
Japanese Unexamined Patent Publication No. 2006-333119 (called Patent Literature 1 hereunder) discloses a circuit technique for testing a clock generation circuit acting as an SSCG. The disclosed technique involves measuring the center frequency for down-spread modulation and comparing the measured frequency with a standard value to diagnose whether the clock generation circuit is normal or defective.
The structure described in paragraphs [0023] through [0025] and in FIG. 1 of the above-cited Patent Literature 1 is as follows: The structure includes an SSCG 2 and a test circuit 1 for use therewith. The SSCG 2 uses a modulated wave signal to modulate a VCO control voltage of a frequency multiplication circuit utilizing an ordinary PLL. In the PLL, a phase comparator detects the phase difference between a reference input signal and a feedback signal obtained by dividing the clock output from a VCO using a frequency divider. The output of the phase comparator is input to a control voltage terminal of the VCO via a charge pump circuit and a low-pass filter. When modulation is not performed, the SSCG outputs the clock of a multiplied frequency stemming from multiplication of the frequency of the reference input signal. The multiplication count is given by the division count of the frequency divider. When modulation is performed, the SSCG outputs a clock of which the frequency fluctuates up and down based on the modulated wave signal in reference to the multiplied frequency. The modulated wave signal is a low-frequency signal such as a triangular wave signal or a sing wave signal that gives the clock frequency of the SSCG a fluctuation cycle and a fluctuation range. The test circuit generates a digital signal indicative of one cycle of the modulated wave by binarizing the modulated wave signal with a comparator and, using the generated digital signal, gets a counter to count the clock of one cycle of the modulated wave. A comparator compares the measured count value with a maximum and a minimum value of the count value of one cycle of the modulated wave, thereby determining whether the clock frequency falls between the upper and the lower limits thereof.
Japanese Unexamined Patent Publication No. 2007-78617 (called Patent Literature 2 hereunder) discloses a circuit technique for testing the SSCG mounted over a semiconductor chip such as ASIC. The structure described in paragraphs [0016] through [0027] and in FIG. 1 of Patent Literature 2 is as follows: A counter A is provided to count an unmodulated clock, and a counter B is provided to count the modulated clock. The counting operations of the counters A and B are started simultaneously by writing a reset instruction value to a reset register. Thereafter, a comparator is used to compare the value of the counter A with that of the counter B. When the value of the counter A reaches a predetermined count value set for the register A, the comparator outputs a stop signal to stop the counting operation of the counter B. After the counting operation of the counter B is stopped by the stop signal, the value of the counter B is placed into the register B when the modulation function is on or into a register C when the modulation function is off. In other words, a series of actions comprised of a reset, a counting operation, and a count result transfer is carried out twice, i.e., when the modulation function is on and when the modulation function is off. Thereafter, the value of the register B and that of the register C are compared, and the result of the comparison is output. In the case of down-spread modulation, the SSCG is diagnosed to be normal if the comparator detects that the value of the register B is smaller than the value of the register C.
In the case of center-spread modulation, even if the clock is normally modulated, the value of the register B becomes equal to that of the register C in the above outlined circuit because the clock frequency is spread in vertically symmetrical fashion about the center frequency in effect when modulation is off. Whether the modulation operation is normally active or is switched off, the value of the register B is equal to that of the register C. This means that the above circuit is incapable of diagnosing whether the SSCG is normal or defective. Thus as described in FIG. 3 and in paragraphs [0033] through [0043] of Patent Literature 2, the bottleneck above is bypassed using a test mode signal that measures the modulation operation for a half-cycle. The test mode signal causes the counter B to count the modulation operation for a half-cycle, and the clock count value on the positive or negative modulation side is stored into the register B. On the other hand, with the modulation operation switched off, the count value for one cycle is placed into the register C. The comparator compares half of the value of the register C with the value of the register B so as to diagnose whether the SSCG is normal. The SSCG is diagnosed to be normal both when the value of the register B is larger than half of the value of the register C in a half-cycle on the positive modulation side and when the value of the register B is smaller than half of the value of the register C in a half-cycle on the negative modulation side.